Comments
Melaine Facon, Director of Codasip’s French Design Centre
CodasipAn open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC-V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects.
With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs.
Michal Siwinski, Group Director, System Realization
Cadence Design SystemsHigh performance processor models are an important part of our virtual prototype solution. The Open Virtual Platforms library of fast processor core models, together with Imperas tools for software analysis, complement the Virtual System Platform to provide an effective solution for system and software development.