Bill McSpadden, Principal VLSI Verification Engineer
Seagate Technology
The Golden RISC-V Reference Model was used as the “go/no-go” model to determine the RTL correct behavior with any discrepancies, bugs or issues with the design, tests, specifications, or test bench.
Charlie Hong-Men Su, CTO & Snr VP
Andes Technology
Imperas virtual platform solutions and tools help in the early phase of SoC and software development, UltraSoC embedded analytics enables hardware-based debug, development and testing. The combination of hardware and simulation solutions will help our mutual customers design the next generation of complex SoCs.