Imperas solutions for early software development have never been more appropriate with development schedules more critical than ever. We believe that simulation-based verification is fast becoming an essential requirement in complex SoCs, and together with advanced debug and analysis tools for many-core and heterogeneous designs will greatly reduce development schedules for next generation devices.
Richard Bohn, Engineering Director
Seagate Technology
The flexibility of RISC-V helps us address domain-specific requirements with custom processors that go beyond the roadmap of the mainstream IP providers.
Designing a high-performance RISC-V processor that achieved up to 3x the performance in critical workloads was no small feat. We needed to balance the features and options with the verification implications. The combined solution of Imperas golden reference models and Valtrix STING has helped us to achieve our verification and schedule goals.