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Imperas to present at Andes RISC-V Con Silicon Valley October 15, 2019

Imperas Demonstrates Andes-Based RISC-V Virtual Platforms for Software Development and Testing

Andes

Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their participation at Andes RISC-V Con 2019 in Silicon Valley.

In order to foster stronger collaboration on RISC-V across the semiconductor industry, Andes RISC‑V CON will focus on this disruptive technology, demonstrating its benefits and identifying commercial strategies.

Imperas will present a technical paper of the advantages of early software development with virtual platforms and tools including extension for timing estimation. Following the announcement that Andes have certified the Instruction Accurate Imperas models of N25 and NX25 additional roadmap support will be highlighted as Imperas supports all the latest Andes RISC-V cores. 

For more information, or to set up meetings with Imperas at Andes DevCon, please email info@imperas.com

Andes RISC-V Con Silicon Valley 2019

When:       Tuesday, October 15, 2019

Where:      David’s Restaurant - 5151 Stars and Stripes Drive, Santa Clara, CA

This event is free to attend but registration is required, please visit Andes RISC-V Con to register.

We look forward to seeing you at Andes RISC-V Con Silicon Valley 2019!

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of their respective holders.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Using OVP Fast Processor Models with OVPsim and other simulators

ARM TrustZone Platform Modeling Application Note

Comments

  • Rick O’Connor, Executive Director

    RISC-V Foundation

    The free and open nature of the RISC-V ISA fosters unprecedented levels of processor innovation. To harness this design freedom, the ecosystem requires robust development tools and the assurance that verification test benches can be developed and validated on supplier-neutral platforms. Imperas’ new riscvOVPsim is an important suite of tools that addresses this challenge.

  • Frankwell Jyh-Ming Lin, President

    Andes Technology

    To support the ever-increasing features of the emerging applications, SoC engineers face the challenges of the design complexity and time-to-market. They need powerful development tools such as fast system simulation for architectural exploration and SW development, emulation for functional verification and system validation, performance optimization, tough bugs tracing and embedded analytics. That is why Andes has worked with some of the partners on V3 AndesCore processors for many years. We are now collaborating with Imperas, Lauterbach, Mentor, and UltraSoC to provide those advanced development tools for our new V5 AndesCore N25 and NX25, and the RISC-V community.