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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

The Hardware Vanishing Point: Someday, Will it All be Software? - Electronic Engineering Journal - Kevin Morris

"The disciplines of hardware and software engineering have always been intertwined and symbiotic - like the yin and yang of some bizarre abstract beast. Software cannot exist without hardware to execute it, of course, and most hardware today is designed in the service of software. The vast majority of systems being designed today involve a mix of both elements working together, with software steadily inheriting more and more of the complexity load.

Let’s think about that for a minute..."

Follow the link to read the full article.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Comments

  • Dr. Luciano Ost

    Embedded Systems and Communications Research Group, University of Leicester

    The lack of electronic design automation (EDA) tools combining model flexibility, and fast and accurate evaluation of performance, power, and reliability is one of the major challenges currently faced by embedded researchers. Even expensive, commercially available tools don't often meet modeling and simulation needs for emerging technologies.The description of processors – i.e., register or gate-level – is rarely available to universities, and commercial licenses are quite expensive. Having free tools with different state-of-the-art processor models allows the exploration of new system architectures.

  • Jérôme Quévremont, vice-chair of OpenHW Cores Task Group

    Thales Research & Technology

    Following the success of the CV32E40P verification, riscvOVPsimCOREV was selected as a reference model for the CVA6 application cores.

    The selection by Imperas of a freeware license model to support CORE-V IPs is a great move towards the adoption of OpenHW industrial-grade CORE-V processor cores by a broader community.