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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Verification 3.0: Grab Your Surfboards, the Next Big Wave is Coming

Highlights of the inaugural Verification 3.0 Innovation Summit in Silicon Valley March 2019.

Verification 3.0 Innovation Summit        Verification 3.0: Grab Your Surfboards, the Next Big Wave is Coming

I’m that rare person, a native (even second generation) Californian, and grew up going to the Southern California beaches during the summers. I earned my Red Cross lifeguarding certificates, and was a pretty good bodysurfer in my youth.  The greatest adrenaline rush I’ve ever had is catching a wave so perfectly that I was in the pipeline, not on a surfboard, but just my body half in, half out of the wave.  

So, when Joe Costello opened up the inaugural Verification 3.0 Innovation Summit (V3IS) with analogies about waves and rip tides and bodysurfing, he was speaking both my languages, verification and oceans. There’s a new verification wave coming, Joe said, building strength and speed, and we should be preparing to have a glorious ride to the shore. The alternative, to not recognize this wave, is to be caught in the rip tide, the undercurrent, with dire consequences .…..

To read the EDACafe Guest blog by Larry Lapides, click here.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Custom Instruction Flow Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Don Smith, Director of Engineering

    MIPS, Inc.

    As the MIPS design and verification teams transition to RISC-V, we see a lot of benefits from adopting the open ISA specification.

    As an IP company, we have a significant focus on the quality and verification of our processor IP deliverables. Imperas are the leaders in RISC-V simulation and verification and, with more than a decade of collaboration, they are the obvious DV partner for MIPS and its new RISC-V offerings.

  • Sandeep Vij, President and CEO

    MIPS Technologies

    We chose Imperas and the Open Virtual Platform technology because of the quality of the models and technology.  We see the positive momentum and leadership position of OVP, and believe this is the best technology for instruction accurate simulation of processor core models.