Jérôme Quévremont, vice-chair of OpenHW Cores Task Group
Thales Research & Technology
Following the success of the CV32E40P verification, riscvOVPsimCOREV was selected as a reference model for the CVA6 application cores.
The selection by Imperas of a freeware license model to support CORE-V IPs is a great move towards the adoption of OpenHW industrial-grade CORE-V processor cores by a broader community.
Allen Baum, Chair of RISC-V Foundation Technical Committee Task Group for Compliance
Esperanto Technologies, Inc.
The work of the RISC-V Compliance Task Group is vital to the success of RISC-V and anyone trying to design or sell RISC-V based products. We welcome the contributions of Imperas and believe that using riscvOVPsim as one of the reference simulators could be highly valuable in the overall compliance effort.