Comments

The Imperas virtual platform solutions for software development, debug and test, along with their open-source models, comprise an excellent methodology for development of embedded software for SoCs based on V5 AndesCore N25 and NX25 RISC-V processors.

A healthy RISC-V ecosystem is critical to the adoption of RISC-V processors. The open RISC-V ISA specifications make it easier for ecosystem companies like Imperas and Andes to collaborate.  Tools such as the Imperas RISC-V models, virtual platforms and software solutions will improve time to market by enabling faster software development, simplifying debug and test, lowering costs and risks and delivering overall increased quality.

We were able to easily merge the Imperas simulator into our automated workflow on our build server for both unit and integration testing.  Running our tests with the production binaries on the simulator enabled us to find bugs that were not found when the software was cross compiled to the x86 Windows environment.

OVPsim beats QEMU in fidelity in CPU simulation - its determinism and speed were pretty impressive. OVPsim configurability is a big advantage as well. We were able to configure low-level CPU features, thanks to comprehensive documentation. I was also enthusiastic about the machine description file. It was easy to connect a missing interrupt signal we needed.

We are all aware of the importance of security, especially in the IoT. Imperas, with their participation in the prpl Foundation, support for the prpl platform, and their high-performance releases, are making important contributions in this arena.

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