Charlie Hong-Men Su, CTO and Senior Vice President
Andes Technology Corp
In commercial semiconductor IP, quality is perhaps the highest priority for successful customer engagements, the extensive test and verification process is best achieved with extensive simulator-based testing. We have already certified the Imperas RISC-V model and simulation technology for Andes N25 and NX25 processors so expect that riscvOVPsim will quickly be adopted as an industry standard reference simulator.
Richard Newell, Associate Technical Fellow
Microchip
The new scalar cryptography extension for RISC-V is designed to be lightweight and to be suitable for 32- and 64-bit base architectures, from embedded, IoT class cores to large, application class cores.
The working group coordinates the member driven contributions and we welcome the Imperas Crypto tests to support the early implementors and adopters.