We were able to easily merge the Imperas simulator into our automated workflow on our build server for both unit and integration testing. Running our tests with the production binaries on the simulator enabled us to find bugs that were not found when the software was cross compiled to the x86 Windows environment.
Kiran Vittal, senior director of Partner Alliances Marketing
Synopsys, Inc.
RISC-V adoption is growing across key market segments as SoC teams explore the flexibility of an open standard ISA for optimized processors.
Our collaboration with Imperas, leveraging Synopsys’ leading simulation and debug solutions, enables our mutual customers to address verification complexities for RISC-V processor cores and quickly achieve coverage convergence.