The flexibility of the RISC-V ISA coupled with the performance of vector extensions is an ideal starting point for AI accelerators for automotive applications.
To address the verification requirement for our next generation of processors, we have developed an optimized verification flow with ImperasDV that our design team set up with detailed configuration options to deliver on their comprehensive verification plans that provides the industry leading quality our customers expect.
Wei Wu, Vice-Chair of RISC-V International P Extension Task Group
PLCT Lab, ISCAS.
By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency.
The Imperas RISC-V reference model provides the ideal starting point to explore and develop software algorithms based on the new RISC-V P extension.