The open ISA of RISC-V is enabling a new wave of processor design innovation across the spectrum of compute requirements in almost all market segments.
High quality processor verification is not a simple task, but the ease of use and configurable approach with RVVI offered by ImperasDV enables the eSOL TRINITY team to support the expert design teams at NSITEXE and other leading adopters of RISC-V in Japan.
Rick O’Connor, President & CEO
OpenHW Group
Fundamental to the OpenHW CORE-V open-source processor family is high-quality verification that has been achieved with the help and support of the dedicated OpenHW members and contributors.
I am excited that Simon [Davidmann, CEO of Imperas] is lending his verification expertise and vision [as Chair] to expand the scope of the OpenHW Verification Task Group to address industry-wide standards and methodologies for all RISC-V adopters.