Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
The RISC-V open standard ISA offers a compatibility framework, yet has built-in flexibility across the specification envelope.
The Imperas contribution of new Crypto extension tests is a welcome addition to the trusted test suite portfolio, supporting implementers with verification of their hardware.
Zbyszek Zalewski, General Manager, Hardware Division
Aldec
The integration of HES with OVPsim enables hardware and software design teams to implement virtual models of processors, memory and peripherals while the RTL modules run in the emulator board. This new integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.