Allen Baum, Chair of RISC-V Foundation Technical Committee Task Group for Compliance
Esperanto Technologies, Inc.
The work of the RISC-V Compliance Task Group is vital to the success of RISC-V and anyone trying to design or sell RISC-V based products. We welcome the contributions of Imperas and believe that using riscvOVPsim as one of the reference simulators could be highly valuable in the overall compliance effort.
Jingliang (Leo) Wang, Co-chair of the OpenHW Group Verification Task Group
Futurewei Technologies
The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores. The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution.
The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.