University of Southern California’s Information Sciences Institute (USC/ISI)
Imperas tools and models provide us with enhanced capabilities to pursue research we could not otherwise achieve with significantly less upfront development effort. The virtual platforms allow us to rapidly explore state-of-the-art prototypes and bridges the gap between hardware and software development.
Simon Davidmann, CEO
Imperas Software
Processor verification is challenging, and yet critical to RISC-V adoption.
ImperasDV is the first commercially available RISC-V processor verification solution, and the achievement of the tight integration with Cadence is key to the successful use of ImperasDV by NSITEXE.