Comments

We are proud to extend our long-standing relationship with Andes, and now announce Andes certification of our OVP models for their 32-bit/64-bit CPU cores, as a reference simulator.

It’s great to be partnering with the leader in processor models and virtual platforms for embedded software development.

The Imperas release of the first commercial simulator that can boot Linux on a RISC-V ISS model represents a significant milestone in the evolution of processors based on the RISC-V RV64GC ISA.A key element of the RISC-V ecosystem is a robust, commercial virtual software development environment and Imperas has delivered on this promise.

We are happy to see this alliance between two major members [Ashling Systems and Imperas Software] of our RISC-V Foundation. RISC-V has the potential to change the way SoCs and embedded systems are developed, and the business models around that.  To achieve this potential, a solid ecosystem is needed, including RISC-V community members working together to build solutions that are greater than the sum of the individual pieces.

Our integration with Imperas brings Ashling closer to our vision to become the provider of a complete RISC-V turnkey solution.

Pages