The defining goal of the OpenHW group is to deliver high quality open source IP cores, by leveraging the leading verification methodologies compatible with the established EDA commercial SoC design flows.
To support our world class IP portfolio, the OpenHW working groups are enabling adoption with tools and software support for CORE-V processors. The Imperas contribution with the new free ISS, riscvOVPsimCOREV will be the foundation reference to all software tasks.
Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture.
The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.