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It’s great to be partnering with the leader in processor models and virtual platforms for embedded software development.

The Imperas release of the first commercial simulator that can boot Linux on a RISC-V ISS model represents a significant milestone in the evolution of processors based on the RISC-V RV64GC ISA.A key element of the RISC-V ecosystem is a robust, commercial virtual software development environment and Imperas has delivered on this promise.

Building out the Mi-V RISC-V ecosystem with the Imperas Extendable Platform Kit (EPK™) is a vital piece of our ecosystem offering as we continue to expand this program and enhance our ability to deliver innovative solutions for customers. The Imperas EPK allows for rapid software development and debugging of corner cases when using Mi-V soft CPUs on Microsemi field programmable gate array (FPGA) products.

To support the ever-increasing features of the emerging applications, SoC engineers face the challenges of the design complexity and time-to-market. They need powerful development tools such as fast system simulation for architectural exploration and SW development, emulation for functional verification and system validation, performance optimization, tough bugs tracing and embedded analytics. That is why Andes has worked with some of the partners on V3 AndesCore processors for many years. We are now collaborating with Imperas, Lauterbach, Mentor, and UltraSoC to provide those advanced development tools for our new V5 AndesCore N25 and NX25, and the RISC-V community.

The Imperas virtual platform solutions for software development, debug and test, along with their open-source models, comprise an excellent methodology for development of embedded software for SoCs based on V5 AndesCore N25 and NX25 RISC-V processors.

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