EW19 Slides on Methodology for Implementation of Custom Instructions in the RISC-V Architecture


One of the key advantages of the new RISC-V Instruction Set Architecture (ISA) is that SoC designers are able to add custom features to the ISA to support their specific applications. There are some risks to doing this, both business and technical, plus there is a need to be able to analyze and optimize the customizations. One approach to customization of RISC-V cores is to use correct-by-construction tools to generate both the compliant and custom pieces of the processor. A second approach is to implement the custom features directly in RTL. With both approaches to implementation, there is still the need for both compliance testing and analytical feedback to enable optimization of the customizations. This paper discusses the alternatives for implementation, and describes an instruction accurate virtual platform methodology for compliance testing and architecture exploration. In this methodology, there is an existing parameterized model of the RISC-V ISA specification, and the custom features are added in an external library. This has the advantage of providing a well-verified compliant model, while at the same time enabling the use of the software debug, analysis and test tools in the virtual platform environment. A case study involving the addition of custom security functionality to a 32-bit RISC-V core is presented, including the compliance testing, memory analysis, function and instruction profiling including timing estimation.