Imperas and OFFIS Paper at ARM TechCon 2016 on Integrating Power Models into Instruction Accurate Virtual Platforms for ARM-base

Abstract: In this paper the current state of embedded software development is discussed. A comparison is made between hardware-based and virtual platform-based methodologies. The management issues of software predictability and delivery risk are discussed. Software verification requirements are introduced. There are many advantages of using Virtual Platform based software development approaches and these are shown. Virtual Platforms and simulation can complement a hardware based software development approach.

The Imperas tool architecture is explained and it is shown how this is used to build a virtual platform and how this enables timing based software simulation to run at upto 500 MIPS whilst using quanta of between 1,000 and 100,000. The control flow between the platform, simulator, intercept library and procesor model is shown.

An approach to Power Modeling with dynamic frequency and voltage scaling (DVFS) is outlined with an introduction on how the Power Model is developed. There are slides with speakers notes on Design-Time, Run-Time, and System-Level Power Analysis and parameters.

A Performance Counter Based Power Model for the Xilinx Zynq ARM-based platform is shown and the calculations for obtaining the dynamic parameters from the Virtual Platform are explained. Results of several analysis runs are provided with many power traces shown. The results of a simple power model for the ARM Cortex-A9 is provided booting Linux and showing a Virtual Power Sensor.