The defining goal of the OpenHW group is to deliver high quality open source IP cores, by leveraging the leading verification methodologies compatible with the established EDA commercial SoC design flows.
To support our world class IP portfolio, the OpenHW working groups are enabling adoption with tools and software support for CORE-V processors. The Imperas contribution with the new free ISS, riscvOVPsimCOREV will be the foundation reference to all software tasks.
Chris Jones, VP product marketing
SiFive, Inc.
The design freedoms of RISC-V and vector extensions are changing the traditional boundaries between the software and hardware phases of SoC development.
The Imperas models of the SiFive cores help developers with SoC architectural exploration across the full flexibility of the SiFive Core IP Portfolio, and support early software development, which is a critical factor in validating new AI solutions.