Imperas and Industry Articles

Hybrid Emulation Takes Center Stage

semiengineering.com

Complex chips require a multitude of verification platforms working in sync, and that’s where the challenges begin.

Types of Hybrid configurations

From mobile to networking to AI applications, system complexity shows no sign of slowing. These designs, which may contain multiple billion gates, must be validated, verified and tested, and it’s no longer possible to just throw the whole thing in a hardware emulator.

For some time, emulation, FPGA-based prototyping, and virtual environments such as simulators have given design and verification teams options when it comes to making sure their designs function properly. Now, because of highly competitive market pressures and system complexity, these technologies are being brought together in a variety of new ways to tackle the enormity of the system verification challenge....

To read the article by Ann Mutschler, click here.

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Hardware-Software Co-Design Reappears

There may be a second chance for co-design, but the same barriers also may get in the way.

semiengineering.com

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on.

What’s different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrated the software, the better the power and performance. Software also adds an element of flexibility, which is essential in many of these designs because algorithms are in a state of almost constant flux……

To read the article by Brian Bailey, click here.

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An evening with the RISC-V Community at the Cambridge Meetup

Highlights of the second RISC-V Meetup in Cambridge, June 2019 co-hosted by UltraSoC & Imperas.

RISC-V Meetup

At our second Cambridge RISC-V Meetup recently, around 60 delegates joined UltraSoC and Imperas Software, to discuss the latest updates on the RISC-V architecture and ecosystem.

In keeping with the theme of previous events, the talks were short and crisp to act as a catalyst for more in-depth conversations during the main social and networking activities over light refreshments. The engaging presentations covered a wide range of topics and touched on open source and commercial projects, hardware and software aspects, plus some activities within academia focused on RISC-V…..

To read the UltraSoC Guest blog by Kevin McDermott, click here.

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Open Source Processors: Fact Or Fiction?

semiengineering.com

Calling an open-source processor free isn’t quite accurate.

The RISC-V Foundation               MIPS Open

 

Open source processors are rapidly gaining mindshare, fueled in part by early successes of RISC-V, but that interest frequently is accompanied by misinformation based on wishful thinking and a lack of understanding about what exactly open source entails.

Nearly every recent conference has some mention of RISC-V in particular, and open source processors in general, whether that includes keynote speeches, technical sessions, and panels. What’s less obvious is that open ISAs are not a new phenomenon, and neither are free, open .......

To read the article by Brian Bailey, click here.

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RISC-V Moving Beyond Academia New Group offers Hardened SoCs

EETimes

 

Zurich – Over the last year or so, we’ve heard many times that ‘this is the moment for RISC-V’. So, this week, I attended the RISC-V workshop in Zurich to get an idea of where it really is at right now. The conclusion: while there is still a lot of background work to be done for RISC-V to go mainstream, the signs are that all the triggers to make it happen are now gradually being released.

The biggest challenge is that RISC-V is still perceived as a hobbyist architecture, and this makes it difficult for mainstream companies to adopt, unless it has deep ecosystem support. It’s not enough to have a cool or disruptive technology. Designers need to provide assurances to their customers that a chip or system fits into their existing design flow and toolchains and can be supported, wherever in the world it may be…….

To read the EETimes article by Nitin Dahad, click here.

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IP Requires System Context At 6/5/3nm

semiengineering.com

At each new process node, gates are free. That opens the door to a lot more IP blocks, and a lot of new challenges.

Driven by each successive generation of semiconductor manufacturing technology, complexity has reached dizzying levels. Every part of the design, verification and manufacturing is more complicated and intense the more transistors are able to be packed onto a die. For these reasons, the entire system must be taken into consideration as a whole…..

To read the article by Ann Mutschler, click here.

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8 RISC-V Companies to Watch

 

These eight companies are developing their own RISC-V technologies and are committing to helping third parties do the same to help push adoption of the open-source chip architecture.

     Design News            The RISC-V Foundation

 

RISC-V (pronounced “risk five”), the open-source architecture for chip design, has been making a lot of noise in the past few years. The open source nature of RISC-V promises to enable companies to create custom chip hardware specifically tailored to their products and devices. 

Now, thanks much in part to the efforts of the RISC-V Foundation, an entire ecosystem of companies has sprung up…

To read the Design News article featuring Imperas Software, click here.

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Optimization Challenges For Safety And Security

semiengineering.com

The road to optimized tradeoff automation is long. Changing attributes along the way can make it even more difficult.

Complexity challenges long-held assumptions. In the past, the semiconductor industry thought it understood performance/area tradeoffs, but over time it became clear this is not so simple. Measuring performance is no longer an absolute. Power has many dimensions including peak, average, total energy and heat, and power and function are tied together.

Design teams are now dealing with the implication of safety and security, which have considerable impact on power/performance/area (PPA) considerations. We are far from understanding the tradeoffs ….

To read the article by Brian Bailey, click here.

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Verification 3.0: Grab Your Surfboards, the Next Big Wave is Coming

Highlights of the inaugural Verification 3.0 Innovation Summit in Silicon Valley March 2019.

Verification 3.0 Innovation Summit        Verification 3.0: Grab Your Surfboards, the Next Big Wave is Coming

I’m that rare person, a native (even second generation) Californian, and grew up going to the Southern California beaches during the summers. I earned my Red Cross lifeguarding certificates, and was a pretty good bodysurfer in my youth.  The greatest adrenaline rush I’ve ever had is catching a wave so perfectly that I was in the pipeline, not on a surfboard, but just my body half in, half out of the wave.  

The Challenge Of RISC-V Compliance

semiengineering.com

Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.

https://semiengineering.com/toward-risc-v-compliance/

The open-standard RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure...

An interesting article by Brian Bailey. To read the article with comments by Simon Davidmann and Kevin McDermott of Imperas Software, click here.

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