The OpenHW Group charter is to deliver high quality processor IP cores for our leading commercial members and open source community adoption.
Central to this goal, the OpenHW Verification Task Group developed and published a DV test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model.
Calista Redmond, CEO
RISC-V International
RISC-V is ideal for the latest compute requirements of single-core embedded controllers through to multicore arrays for high performance computing applications.
Companies like Imperas are leading the charge in making SoC design and verification flow easier to further accelerate the mass adoption of RISC-V.