As one of the first IP providers for RISC-V cores, we see the importance of compliance as the RISC-V ecosystem develops. riscvOVPsim is a solid starting point for developers looking for a RISC V ISS (Instruction Set Simulator) for test and verification.
Shubhodeep Roy Choudhury, Managing Director & Co-founder
Valtrix Systems
Ideally any test should provide a clear pass or fail indication. In the case of RISC-V processor DV this is achieved with a comparison against a quality reference model.
STING helps generate portable, architecturally correct and self-checking tests targeted at the corner-case scenarios by automating the comparison of the DUT against the Imperas reference model results.