All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.
Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.
Gunar Schirner
Associate Professor, Northeastern University, Boston, USA
I find Imperas tools and models invaluable for my research and my course, High Level Design of Hardware Software Systems. My students can now explore and command state-of-the-art prototyping technology for complex systems.