Comments
Melaine Facon, Director of Codasip’s French Design Centre
CodasipAn open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC-V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects.
With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs.
Richard Bohn, Engineering Director
Seagate TechnologyThe flexibility of RISC-V helps us address domain-specific requirements with custom processors that go beyond the roadmap of the mainstream IP providers.
Designing a high-performance RISC-V processor that achieved up to 3x the performance in critical workloads was no small feat. We needed to balance the features and options with the verification implications. The combined solution of Imperas golden reference models and Valtrix STING has helped us to achieve our verification and schedule goals.