Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture.
The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.
Calista Redmond, CEO
RISC-V International
RISC-V is ideal for the latest compute requirements of single-core embedded controllers through to multicore arrays for high performance computing applications.
Companies like Imperas are leading the charge in making SoC design and verification flow easier to further accelerate the mass adoption of RISC-V.