Comments
Melaine Facon, Director of Codasip’s French Design Centre
CodasipAn open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC-V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects.
With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs.
Don Smith, Vice President Engineering
MIPS, Inc.At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors.
As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.