The pace of innovation in markets such as the latest 5G communication networks and infrastructure offers many opportunities for new domain-specific SoC solutions.
As a leading supplier of silicon IP, we fully appreciate the role of the ecosystem in supporting our lead customers in delivering new devices to market. We are pleased Imperas have now released the first Catapult RISC-V CPU Imperas reference model for the IMG RTXM-2200, which provides our mutual customers a proven path to accelerate projects to market.
Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project
ETH Zurich
RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.