Comments
Jingliang (Leo) Wang, Co-chair of the OpenHW Group Verification Task Group
Futurewei TechnologiesThe UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores. The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution.
The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.
Tony King-Smith, EVP Marketing
Imagination TechnologiesWe are delighted to be working with Imperas to deliver the fastest Instruction Accurate (IA) simulation solution for our many MIPS partners. We have been impressed how Imperas’ simulation technology significantly outperforms other commonly-used solutions. Faster simulation results in more tests being run, and therefore higher quality software being developed - and that is good news for our extensive MIPS ecosystem community. Since acquiring MIPS, Imagination has committed to working more closely with innovative partners like Imperas to deliver superior CPU modelling solutions. As a result, we are confident our MIPS licensees and many software ecosystem partners will have access to the best tools in the industry, enabling them to create the best possible software and products.