Processor verification is challenging, and yet critical to RISC-V adoption.
ImperasDV is the first commercially available RISC-V processor verification solution, and the achievement of the tight integration with Cadence is key to the successful use of ImperasDV by NSITEXE.
Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture.
The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.