Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project
ETH Zurich
RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.
Richard Newell, Associate Technical Fellow
Microchip
The new scalar cryptography extension for RISC-V is designed to be lightweight and to be suitable for 32- and 64-bit base architectures, from embedded, IoT class cores to large, application class cores.
The working group coordinates the member driven contributions and we welcome the Imperas Crypto tests to support the early implementors and adopters.