Kiran Vittal, senior director of Partner Alliances Marketing
Synopsys, Inc.
RISC-V adoption is growing across key market segments as SoC teams explore the flexibility of an open standard ISA for optimized processors.
Our collaboration with Imperas, leveraging Synopsys’ leading simulation and debug solutions, enables our mutual customers to address verification complexities for RISC-V processor cores and quickly achieve coverage convergence.
Hideki Sugimoto, CTO
NSITEXE, Inc.
New design innovations with RISC-V offer great potential in automotive applications, but achieving the extensive quality standards are critical for success.
The verification requirements to achieve the ASIL D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables.