Processor verification is challenging, and yet critical to RISC-V adoption.
ImperasDV is the first commercially available RISC-V processor verification solution, and the achievement of the tight integration with Cadence is key to the successful use of ImperasDV by NSITEXE.
Dr. Charlie Su, President and CTO
Andes Technology Corp.
RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations.
The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.