Comments
Frankwell Jyh-Ming Lin, President
Andes TechnologyTo support the ever-increasing features of the emerging applications, SoC engineers face the challenges of the design complexity and time-to-market. They need powerful development tools such as fast system simulation for architectural exploration and SW development, emulation for functional verification and system validation, performance optimization, tough bugs tracing and embedded analytics. That is why Andes has worked with some of the partners on V3 AndesCore processors for many years. We are now collaborating with Imperas, Lauterbach, Mentor, and UltraSoC to provide those advanced development tools for our new V5 AndesCore N25 and NX25, and the RISC-V community.
Jérôme Quévremont, vice-chair of OpenHW Cores Task Group
Thales Research & TechnologyFollowing the success of the CV32E40P verification, riscvOVPsimCOREV was selected as a reference model for the CVA6 application cores.
The selection by Imperas of a freeware license model to support CORE-V IPs is a great move towards the adoption of OpenHW industrial-grade CORE-V processor cores by a broader community.