Jingliang (Leo) Wang, Co-chair of the OpenHW Group Verification Task Group
Futurewei Technologies
The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores. The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution.
The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.
Hirohiko Ono, Senior Manager of the MCU Tools Marketing Department
Renesas Electronics Corporation
Imperas with its OVP Fast Processor Models is addressing key issues in software development for embedded systems. We are happy to work with Imperas to ensure that high quality models are easily available to our worldwide customers, helping them to develop and test software faster and more easily using virtual platforms.