At Ventana, our teams of developers are building the foundational processor IP and chiplet building blocks that will enable a step change in performance for the most demanding compute workload markets.
Our verification strategy is to exercise the RISC-V based processors across the most demanding scenarios and are using Imperas RISC-V vector test suites in addition to the Imperas golden reference model in our verification environment.
Martin Baker, Senior Manager
Automotive Business Unit of Renesas Electronics America.
Imperas is launching some very interesting approaches to processor modeling and software testing. Historically processor models have been used in relatively small numbers, despite their enormous benefits. The Imperas business model has the potential to make processor modeling an affordable approach used widely across the industry.