Bill McSpadden, Principal VLSI Verification Engineer
Seagate Technology
The Golden RISC-V Reference Model was used as the “go/no-go” model to determine the RTL correct behavior with any discrepancies, bugs or issues with the design, tests, specifications, or test bench.
Jérôme Quévremont, vice-chair of OpenHW Cores Task Group
Thales Research & Technology
Following the success of the CV32E40P verification, riscvOVPsimCOREV was selected as a reference model for the CVA6 application cores.
The selection by Imperas of a freeware license model to support CORE-V IPs is a great move towards the adoption of OpenHW industrial-grade CORE-V processor cores by a broader community.