Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture.
The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.
Martin Baker, Senior Manager
Automotive Business Unit of Renesas Electronics America.
Imperas is launching some very interesting approaches to processor modeling and software testing. Historically processor models have been used in relatively small numbers, despite their enormous benefits. The Imperas business model has the potential to make processor modeling an affordable approach used widely across the industry.