Comments
Philippe Luc, Verification Director
CodasipImperas are the pioneers in simulation technology and processor verification for RISC-V.
While processor verification is not a new problem, there are many RISC-V suppliers, with customization and various levels of verification or conformance: customers are legitimately concerned about both quality and fragmentation. Codasip is very proud of our rigorous approach to verification– using Imperas as an important part of our quality process furthers extend our differentiation. The Imperas independence, reputation and technical strength provides our customers with further reassurance in our ‘best in class’ RISC-V processors.
Hiroyasu Hasegawa, CTO
hd Lab, JapanFor our SystemC training courses, we want the attendees to focus on building SystemC models, and how to use those models. By using OVP Fast Processor Models, which work easily in SystemC virtual platforms, students do not have to worry about processor models, and are able to get the most out of our courses. The OVP models work well in our SystemC environment and also with other SystemC tools. We are excited to be able to expand our design service offerings in virtual platforms to our customers.