High quality IP is an important deliverable that others can build on, but developers need more than just processor RTL to support high quality implementations.
All embedded software is closely related to the IP core it will run on; thus, an accurate ISS reference model is essential for all HW and SW adopters. riscvOVPsimCOREV is the key starting point for the support of the OpenHW CORE-V cores by the ecosystem.
Allen Baum, Chair of the RISC-V International Architecture Test SIG
Esperanto Technologies, Inc.
The RISC-V open standard ISA offers a compatibility framework, yet has built-in flexibility across the specification envelope.
The Imperas contribution of new Crypto extension tests is a welcome addition to the trusted test suite portfolio, supporting implementers with verification of their hardware.