Comments
Charlie Hong-Men Su, CTO and Senior Vice President
Andes Technology CorpIn commercial semiconductor IP, quality is perhaps the highest priority for successful customer engagements, the extensive test and verification process is best achieved with extensive simulator-based testing. We have already certified the Imperas RISC-V model and simulation technology for Andes N25 and NX25 processors so expect that riscvOVPsim will quickly be adopted as an industry standard reference simulator.
Melaine Facon, Director of Codasip’s French Design Centre
CodasipAn open verification standard such as RVVI provides the essential framework and guidelines to configure the test environment for RISC-V and allows the flexibility necessary to address all aspects of a modern processor yet maintain a common base that allows verification IP reuse across projects.
With the latest additions to Imperas’ tools processor DV teams can pre-test system level integrations and cover the next level of complex asynchronous events with virtual components integrated into the test bench. These guidelines both support entry level verification and also enable experts to build compressive test environments for the most complex RISC-V designs.