OVP is widely used by our customers, who demanded the integration with CyberWorkBench. This integration significantly broadens CWB's HW/SW co-verification support. We were also very impressed with Imperas technical support helping us achieve this integration extremely quickly and efficiently.
Dr. Charlie Su, President and CTO
Andes Technology Corp.
RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations.
The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.