Our new Aptiv Generation of cores pushes the boundaries in performance and efficiency. Having MIPS-Verified support from Imperas and OVP, a leading supplier of high-quality, fast processor core models, enables our customers to get started immediately with designs based on the Aptiv Generation cores.
Wei Wu, Vice-Chair of RISC-V International P Extension Task Group
PLCT Lab, ISCAS.
By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency.
The Imperas RISC-V reference model provides the ideal starting point to explore and develop software algorithms based on the new RISC-V P extension.