Bill McSpadden, Principal VLSI Verification Engineer
Seagate Technology
The Imperas Golden RISC-V Reference Model helped us find many bugs in our cores.
However, the RISC-V architectural tests yielded no bugs, which is expected since the architectural tests are a subset of full verification.
Arjan Bink, chair of OpenHW Cores Task Group
Silicon Laboratories
High quality IP is an important deliverable that others can build on, but developers need more than just processor RTL to support high quality implementations.
All embedded software is closely related to the IP core it will run on; thus, an accurate ISS reference model is essential for all HW and SW adopters. riscvOVPsimCOREV is the key starting point for the support of the OpenHW CORE-V cores by the ecosystem.