Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project
ETH Zurich
RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.
Premal Buch, VP Software
Altera
Given the wide variety of customer applications for our SoC FPGAs, our software stacks require rigorous and comprehensive testing. Imperas' M*SDK has proven to be an outstanding environment for the validation and analysis of operating systems, drivers and firmware. Verification using the Imperas solution not only accelerates software bug discovery, but also provides a rapid understanding of the root cause of problems.