All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.
Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.
Philippe Berger, CEO
Dolphin Design
Our verification methodology for the Panther DSP/AI Accelerator IP needs to address not just the full range of the current configuration options but also the roadmap for Panther.
ImperasDV is the cornerstone of our simulation-based DV strategy, with the Imperas golden reference model, scoreboard, verification IP, functional coverage analysis and debug efficiency.