Comments
Don Smith, Vice President Engineering
MIPS, Inc.At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors.
As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.
Rick O’Connor, President & CEO
OpenHW GroupThe OpenHW Verification Task Group contributors are pioneers in the drive to advance the quality of open-source hardware IP ready for mainstream adoption – quality deliverables are the hallmark of any trusted IP provider, commercial or open source.
OpenHW membership growth over the past three years is expanding the roadmap of IP core projects dramatically, with projects addressing the needs for application class devices supporting Linux, embedded security, and compute intensive applications with custom instructions. The RVVI open standard and flexible methodology significantly helps the OpenHW Verification Task Group members and contributors with efficient and quality verification for the full range of CORE-V IP projects.