Imperas in the News

Andes partners with EDA tool vendors for more RISC-V SoC support

Andes Technology

Andes partners with EDA tool vendors for more RISC-V SoC support

Andes Technology announces its partnership with several tools vendors including Imperas, Lauterbach, Mentor, a Siemens Business, and UltraSoC to bring their system-on-chip (SoC) development environments to Andes V5 processors and the RISC-V community.

To read the Andes press release, click here.

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How To Handle Concurrency

Semiconductor Engineering

How To Handle Concurrency.

The recent article in Semiconductor Engineering by Brian Bailey on Handling Concurrency, includes discussion from Simon Davidmann of Imperas.

System complexity is skyrocketing. The evolution of processing architectures has solved many problems within a chip, but for each problem solved another one was created. Concurrency is one of those issues, and it has been getting much more attention lately.

To read the article, click here.

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Simon Davidmann: A re-energized Imperas Tutorial at DAC 2017

Peggy Aycinena (freelance journalist and Editor of EDA Confidential at www.aycinena.cominterviewed Simon Davidmann (Imperas CEO) on EDACafe about the recent Imperas Tutorial at DAC 2017 on Virtual Platform Based Linux Bring Up Methodology. Peggy Aycinena.

The discussion was wide-ranging and they also covered IP, operating systems, embedded / hardware-dependent software, and more.

To read the interview on EDACafe, please visit: Link to EDACafe.

For slides from the DAC tutorial, see: http://www.imperas.com/tutorial-from-dac-2017-virtual-platform-based-linux-bring-up-methodology

Five Minutes With... - Embedded Computing Design - Larry Lapides

Five Minutes With… Larry Lapides, vice president, Imperas

The best CPU architecture in the world won’t do you much good if the ecosystem falls flat.

RISC-V, the new kid on the block when it comes to instruction-set architectures (ISAs), is up against that stumbling block right now - it needs tools to not just survive, but to thrive.

In this week's Five Minutes with…discussion, Rich Nass of Embedded Computing Design and Larry Lapides, VP of Imperas talked about the present and future of the RISC-V ecosystem  ... click here to read more and listen to the audio interview.

Click here to go directly to the interview on YouTube.

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Heterogeneous System Challenges Grow

Semiconductor Engineering

How to make sure different kinds of processors will work in an SoC.

Ann Steffora Mutschler of Semiconductor Engineering has written an article on the challenges of heterogenous systems.

As more types of processors are added into SoCs—CPUs, GPUs, DSPs and accelerators, each running a different OS—there is a growing challenge to make sure these compute elements interact properly with their neighbors.

Adding to the problem is this mix of processors and accelerators varies widely between different markets and applications. In mobile there are CPUs, GPUs, video and crypto processors. In automotive, there may be additional vision processing accelerators. In networking and servers there are various packet processing and cryptography accelerators. Server applications traditionally have relied on general-purpose CPU, but the future brings more dedicated acceleration engines, which may be customized for specific applications and may be implemented using FPGAs.

Rethinking Verification For Cars

Semiconductor Engineering

First of two parts: How the car industry can improve reliability.

Ann Steffora Mutschler of Semiconductor Engineering has written an article on how to improve reliability in automotive.

As the amount of electronic content in a car increases, so does the number of questions about how to improve reliability of those systems.

Unlike an IoT device, which is expected last a couple of years, automotive electronics fall into a class of safety-critical devices. There are standards for verifying these devices, new test methodologies, and there is far more scrutiny about how all of this happens.

“We are moving from ADAS to autopilot, from autopilot to autonomous driving,” said...

To read the article, click here.

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Hypervisors: Help Or Hindrance?

Almost everything is a tradeoff and tipping the scales is usually influenced by the end product goals. Hypervisors have a few such parameters.

Brian Bailey is Technology Editor/EDA for Semiconductor Engineering and has written an interesting article related to Hypervisors.

Hypervisors are seeing an increased level of adoption, but do they help or hinder the development and verification process? The answer may depend on your perspective.

In the hardware world, system-level integration is rapidly becoming a roadblock in the development process. While each of the pieces may be known to work separately, as soon as they are put together, the interactions between them can create a number of problems. The industry is working to come up with some tools and methodologies that constrain this problem.

In the software world, they are taking a different approach. They are using a hypervisor to create well-defined interfaces between the individual software blocks, ensuring that one cannot disturb another. This enables applications to be built that are more robust, provide a significant increase in security, allow for staged development and enables the controlled intermixing of attributes of a real time environment, with a more flexible operating system environment such as Linux.

Will Hypervisors Protect Us?

They may not be a silver bullet, but they are a good first step when it comes to securing cars and the Internet of Things. Problems start when people believe the job is complete.

Brian Bailey is Technology Editor/EDA for Semiconductor Engineering and has written a very informative article on issues related to Hypervisors.

Another day, another car hacked and another report of a data breach. The lack of security built into electronic systems has made them a playground for the criminal world, and the industry must start becoming more responsive by adding increasingly sophisticated layers of protection. In this, the first of a two-part series, Semiconductor Engineering examines how hypervisors are entering the embedded world.

Simon Davidmann, CEO of Imperas, frames the ...

To read the article, click here.

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Silicon Without Software is Just Sand - EE Journal - Amelia Dalton

Embedded Software Development with Virtual Platforms

Shifting Left with Imperas

No one builds a chip without simulation, right? In this week’s Fish Fry, Amelia Dalton of Electronic Engineering Journal takes a closer look at the value of virtual prototypes to simulate embedded software. Simon Davidmann (CEO - Imperas) and Amelia chat about about why Simon thinks no one should design embedded software without simulation, and the benefits of using virtual platforms to develop a verification and test environment.

 

Follow the link to listen to the interview / Fish Fry....

[Amelia's Fish Fry's are one-on-one audio interviews  / podcasts with industry experts / executives about topical issues and technologies.]

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Imperas Paper at TVS DVClub 2016 Software Verification for Low Power Safety Critical Systems

<b>Abstract</b>:
<p>In November 2016, Simon Davidmann of Imperas gave a talk on how Imperas technology is being used for Timing Analysis, Power Analysis and Fault Simulation
to assist with Software Verification. Here are the slides. The talk was split into two sections.</p>
<p>The first section covers software verification for embedded systems and provides an overview of the challenges of many processors
in current embedded systems. It leads into the requirements for software verification and introduces specific embedded software development issues. It then
explains using simulation / virtual platforms and advanced tools to make embedded software development easier, quicker, and more affordable.</p>
<p>There are explanations of how simulation can be used with continuous integration and other modern software development practices.</p>
<p>The second section of the talk introduces the issues related to low power and how to use simulation to get a handle on the affects of software on low power design.
</p>
<p>Imperas is collaborating with several institutes and universities around the world and these collaborations are explored.</p>
<p>The use of Imperas Instruction Accurate simulation used for Timing Analysis, Power Analysis and Fault Simulation are discussed with examples and case studies.</p>

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