Zbyszek Zalewski, General Manager, Hardware Division
Aldec
The integration of HES with OVPsim enables hardware and software design teams to implement virtual models of processors, memory and peripherals while the RTL modules run in the emulator board. This new integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.
Don Smith, Director of Engineering
MIPS, Inc.
As the MIPS design and verification teams transition to RISC-V, we see a lot of benefits from adopting the open ISA specification.
As an IP company, we have a significant focus on the quality and verification of our processor IP deliverables. Imperas are the leaders in RISC-V simulation and verification and, with more than a decade of collaboration, they are the obvious DV partner for MIPS and its new RISC-V offerings.